Portrait of Akira Jinguji AKIRA JINGUJI

Journals (peer-reviewed)

  1. H. Tanabe, A. Jinguji, A. Takahashi, "Weakly guiding approximation of a three-dimensional waveguide model for extreme ultraviolet lithography simulation (TBA)" Manuscript in preparation.
  2. H. Tanabe, A. Jinguji, A. Takahashi, "Pre-training CNN for fast EUV lithography simulation including M3D effects (TBA)" Manuscript in preparation.
  3. H. Tanabe, A. Jinguji, A. Takahashi, "Accelerating extreme ultravolet lithography simulation with weakly guiding approximation and source position dependent transmission cross coefficient formula" Journal of Micro/Nanopatterning, Mater. Metrol (JM3), (accepted).
  4. H. Tanabe, A. Jinguji, A. Takahashi, "Evaluation of Convolutional Neural Network for Fast Extreme Ultraviolet Lithography Simulation using Imec 3 nm Node Mask Patterns" Journal of Micro/Nanopatterning, Materials, and Metrology, Vol. 22, Issue 2, 024201, June 2023.
  5. T. Senoo, A. Jinguji, R. Kuramochi, H. Nakahara, "A Multilayer Perceptron Training Accelerator using Systolic Array" IEICE Transactions on Information and Systems, Vol. E105-D, No. 12, pp.2048-2056, December 2022.
  6. A. Jinguji, S. Sato, H. Nakahara, "Weight Sparseness for a Feature-Map-Split-CNN Toward Low-Cost Embedded FPGAs" IEICE Transactions on Information and Systems, Vol. E104-D, No. 12, pp. 2040-2047, December 2021.
  7. A. Jinguji, S. Sato, H. Nakahara, "An FPGA Realization of a Random Forest with k-means Clustering using a High-level Synthesis Design" IEICE Transactions on Information and Systems, Vol. E101-D, No. 2, pp. 354-362, February 2018.

International Conferences (peer-reviewed)

  1. A. Jinguji, K. Sano, "A Comparative Survey of GPUs and ASICs for AI Acceleration" R-CCS Symposium 2025 (Poster).
  2. A. Jinguji, Collaborators, "A Many-core Architecture for an Ensemble Ternary Neural Network Toward High-Throughput Inference" (TBA)
  3. T. Senoo, R. Kayanoma, A. Jinguji, and H. Nakahara, "A Light-weight Vision Transformer toward Near-Memory Computation on an FPGA" Applied Reconfigurable Computing International Symposium, (ARC 2023), pp. 338-353, September 2023.
  4. H. Tanabe, A. Jinguji, A. Takahashi, "Evaluation of CNN for fast EUV lithography simulation using iN3 logic mask patterns." Proc. SPIE 12495, DTCO and Computational Patterning II, 12495-55, March, 2023.
  5. T. Senoo, A. Jinguji, R. Kuramochi, H. Nakahara, "A Multilayer Perceptron Training Accelerator using Systolic Array" IEEE Asia Pacific Conf. on Circuits and Systems (APCCAS2021), pp. 77-80, Online, November 2021.
  6. Y. Sada, N. Soga, M. Shimoda, A. Jinguji, S. Sato, H. Nakahara, "Fast Monocular Depth Estimation on an FPGA" IEEE International Parallel and Distributed Processing Symposium Workshops (RAW2020), pp. 143-146, Online, May, 2020.
  7. A. Jinguji, S. Sato, H. Nakahara, "Tiny On-Chip Memory Realization of Weight Sparseness Split-CNNs on Low-end FPGAs" IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM2020), p. 229, Online, May 2020.
  8. H. Nakahara, Q. Zhiqiang, A. Jinguji, W. Luk, "R2CNN: Recurrent Residual Convolutional Neural Network on FPGA" ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA2020), p. 319, Seaside, California, USA, February 2020.
  9. Y. Sada, M. Shimoda, A. Jinguji, H. Nakahara, "A Dataflow Pipelining Architecture for Tile Segmentation with a Sparse MobileNet on an FPGA" International Conference on Field-Programmable Technology (FPT2019), pp. 267-270, Tianjin, China, December 2019.
  10. A. Jinguji, Y. Sada, H. Nakahara, "Real-Time Multi-Pedestrian Detection in Surveillance Camera using FPGA" International Conference on Field-Programmable Logic and Applications (FPL2019), pp. 424-425, Barcelona, Spain, September 2019.
  11. H. Nakahara, Y. Sada, M. Shimoda, K. Sayama, A. Jinguji, S. Sato, "FPGA-based Training Accelerator Utilizing Sparseness of Convolutional Neural Network" International Conference on Field-Programmable Logic and Applications (FPL2019), pp. 180-186, Barcelona, Spain, September 2019.
  12. H. Nakahara, A. Jinguji, M. Shimoda, S. Sato, "An FPGA-based Fine-Tuning Accelerator for a Sparse CNN" ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA2019), p. 186, Seaside, California, USA, February 2019.
  13. A. Jinguji, T. Fujii, S. Sato, H. Nakahara, "An FPGA Realization of OpenPose based on a Sparse Weight Convolutional Neural Network" International Conference on Field-Programmable Technology (FPT2018), pp. 313-316, Naha, Okinawa, Japan, December 2018.
  14. H. Nakahara, A. Jinguji, S. Sato, T. Sasao, "A Random Forest using a Multi-valued Decision Diagram on an FPGA" IEEE International Symposium on Multiple-Valued Logic (ISMVL2017), pp. 266-271, Novi Sad, Serbia, May 2017.
  15. H. Nakahara, A. Jinguji, T. Fujii, S. Sato, "An Acceleration of a Random Forest Classification using Altera SDK for OpenCL" International Conference on Field-Programmable Technology (FPT2016), pp. 285-288, Xian, China, December 2016.

Awards

  1. IEICE Technical Committee on Reconfigurable Systems, Young Researcher Award, "FPGA Implementation of Multi-core Neural Networks via High-level Synthesis" Institute of Electronics, Information and Communication Engineers, January 2022.
  2. Design Gaia Outstanding Poster Presentation Award, "FPGA Accelerator for Image Recognition Using gMLP" IEICE Design Gaia Poster Award Selection Committee, December 2021.
  3. IEICE Technical Committee on Reconfigurable Systems, Young Researcher Award, "Feature-Map Separable Convolution for Memory-Efficient FPGA Image Recognition" Institute of Electronics, Information and Communication Engineers, January 2019.

Research Grants

  1. Google Silicon Research Grant, Co-Principal Investigator (Takuya Kojima, Akira Jinguji), FY2024–FY2025 (Reiwa 6–7), "Sparsity-aware Coarse-grained Reconfigurable Accelerator" Award total: USD 30,000.
  2. KAKENHI Grant-in-Aid for Scientific Research (B), Co-Investigator (Hiroki Nakahara, Akira Jinguji), FY2024–FY2028 (Reiwa 6–10), "Dedicated Hardware for Binary Vision Transformers" Award total: JPY 13,000,000.
  3. Industry-sponsored collaborative research (NDA), "April 2023 – March 2024" Scope and funding confidential under non-disclosure agreement.
  4. Tokyo Tech School of Engineering Assistant Professor Incentive Research Fund, Principal Investigator, "Designing High-efficiency Sparse Matrix Engines for Deep Learning" Total budget: JPY 550,000, October 2022 – March 2023.
  5. Industry-sponsored collaborative research (NDA), "April 2022 – March 2023" Scope and funding confidential under non-disclosure agreement.
  6. JSPS Research Fellowship (DC1) Grant, Principal Investigator, "Realizing Fast CNN Systems through Combined Static and Dynamic Pruning" Total budget: JPY 3,100,000, April 2020 – March 2022.