AKIRA JINGUJI

About Me

Affiliations

  • Assistant Professor of Takahashi Laboratory, Tokyo Institute of Technology

  • President of Spice Engine Co., Ltd.

Research Fields

  • Application and Optimization of Machine Learning in Embedded Systems

Keywords

  • FPGA, Computer Architecture, Machine Learning

Experiences

  • 2022-Current Tokyo Institute of Technology (assistant professor)

  • 2020-2022 Tokyo Institute of Technology (doctor student, graduated)

  • 2018-2020 Tokyo Institute of Technology (master student, graduated)

  • 2017-2018 Sikmi Inc. (full-time engineer, retired)

  • 2013-2017 Tokyo Institute of Technology (bachelor student, graduated)

Journals

  1. T. Senoo, A. Jinguji, R. Kuramochi, H. Nakahara,
    "A Multilayer Perceptron Training Accelerator using Systolic Array",
    IEICE Transactions on Information and Systems, (accepted), 2022.

  2. A. Jinguji, S. Sato, H. Nakahara,
    "Weight Sparseness for a Feature-Map-Split-CNN Toward Low-Cost Embedded FPGAs",
    IEICE Transactions on Information and Systems, Vol. E104-D, No. 12, pp. 2040-2047, December 2021.

  3. A. Jinguji, S. Sato, H. Nakahara,
    "An FPGA Realization of a Random Forest with k-means Clustering using a High-level Synthesis Design",
    IEICE Transactions on Information and Systems, Vol. E101-D, No. 2, pp. 354-362, February 2018.

Conferences

  1. T. Senoo, A. Jinguji, R. Kuramochi, H. Nakahara,
    "A Multilayer Perceptron Training Accelerator using Systolic Array",
    IEEE Asia Pacific Conf. on Circuits and Systems (APCCAS2021), pp.
    77-80, Online, November 2021.

  2. Y. Sada, N. Soga, M. Shimoda, A. Jinguji, S. Sato, H. Nakahara,
    "Fast Monocular Depth Estimation on an FPGA",
    IEEE International Parallel and Distributed Processing Symposium Workshops (RAW2020), pp. 143-146, Online, May, 2020.

  3. A. Jinguji, S. Sato, H. Nakahara,
    "Tiny On-Chip Memory Realization of Weight Sparseness Split-CNNs on Low-end FPGAs",
    IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM2020), p. 229, Online, May 2020.

  4. H. Nakahara, Q. Zhiqiang, A. Jinguji, W. Luk,
    "R2CNN: Recurrent Residual Convolutional Neural Network on FPGA",
    ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA2020), p. 319, Seaside, California, USA, February 2020.

  5. Y. Sada, M. Shimoda, A. Jinguji, H. Nakahara,
    "A Dataflow Pipelining Architecture for Tile Segmentation with a Sparse MobileNet on an FPGA",
    International Conference on Field-Programmable Technology (FPT2019), pp. 267-270, Tianjin, China, December 2019.

  6. A. Jinguji, Y. Sada, H. Nakahara,
    "Real-Time Multi-Pedestrian Detection in Surveillance Camera using FPGA",
    International Conference on Field-Programmable Logic and Applications (FPL2019), pp. 424-425, Barcelona, Spain, September 2019.

  7. H. Nakahara, Y. Sada, M. Shimoda, K. Sayama, A. Jinguji, S. Sato,
    "FPGA-based Training Accelerator Utilizing Sparseness of Convolutional Neural Network",
    International Conference on Field-Programmable Logic and Applications (FPL2019), pp. 180-186, Barcelona, Spain, September 2019.

  8. H. Nakahara, A. Jinguji, M. Shimoda, S. Sato,
    "An FPGA-based Fine-Tuning Accelerator for a Sparse CNN",
    ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA2019), p. 186, Seaside, California, USA, February 2019.

  9. A. Jinguji, T. Fujii, S. Sato, H. Nakahara,
    "An FPGA Realization of OpenPose based on a Sparse Weight Convolutional Neural Network",
    International Conference on Field-Programmable Technology (FPT2018), pp. 313-316, Naha, Okinawa, Japan, December 2018.

  10. H. Nakahara, A. Jinguji, S. Sato, T. Sasao,
    "A Random Forest using a Multi-valued Decision Diagram on an FPGA",
    IEEE International Symposium on Multiple-Valued Logic (ISMVL2017), pp. 266-271, Novi Sad, Serbia, May 2017.

  11. H. Nakahara, A. Jinguji, T. Fujii, S. Sato,
    "An Acceleration of a Random Forest Classification using Altera SDK for OpenCL",
    International Conference on Field-Programmable Technology (FPT2016), pp. 285-288, Xian, China, December 2016.

Japanese Domestic Conferences

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